Method and apparatus for a zero voltage processor sleep state

A processor comprising:

• a plurality of cores, wherein each of the plurality of cores include,
• one or more execution units,
• a plurality of caches, and
• a power management logic to cause the processor to,
• enter a low power state in which a clock signal provided to the one or more execution units is gated, wherein the power management logic to further cause the clock signal provided to the processor to be gated in response to executing a power-save instruction,
• enter a sleep state in which the frequency of the clock signal and a voltage provided to the one or more execution units is reduced in response to determining that a low power mode is to be entered.