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US 2012/0072710 A1Published application
Direct scatter loading of executable software image from a primary processor to one or more secondary processor in a multi-processor system
AssigneeQUALCOMM Incorporated
InventorsNitin Gupta, Daniel H. Kim, Igor Malamant, Steve Haehnichen
Life of this patent
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Abstract
In a multi-processor system, an executable software image including an image header and a segmented data image is scatter loaded from a first processor to a second processor. The image header contains the target locations for the data image segments to be scatter loaded into memory of the second processor. Once the image header has been processed, the data segments may be directly loaded into the memory of the second processor without further CPU involvement from the second processor.
Claims24
A multi-processor system comprising:
- a secondary processor comprising system memory and a hardware buffer for receiving at a least a portion of an executable software image, the secondary processor comprising a scatter loader controller for loading the executable software image directly from the hardware buffer to the system memory;
- a primary processor coupled with a memory, the memory storing the executable software image for the secondary processor;
- and
- an interface communicatively coupling the primary processor and the secondary processor via which the executable software image is received by the secondary processor.
1 more element
A method comprising:
- receiving at a secondary processor, from a primary processor via an inter-chip communication bus, an image header for an executable software image for the secondary processor that is stored in memory coupled to the primary processor, the executable software image comprising the image header and at least one data segment;
- processing, by the secondary processor, the image header to determine at least one location within system memory to which the secondary processor is coupled to store the at least one data segment;
- receiving at the secondary processor, from the primary processor via the inter-chip communication bus, the at least one data segment;
- and
- loading, by the secondary processor, the at least one data segment directly to the determined at least one location within the system memory.
2 more elements
An apparatus comprising:
- means for receiving at a secondary processor, from a primary processor via an inter-chip communication bus, an image header for an executable software image for the secondary processor that is stored in memory coupled to the primary processor, the executable software image comprising the image header and at least one data segment;
- means for processing, by the secondary processor, the image header to determine at least one location within system memory to which the secondary processor is coupled to store the at least one data segment;
- means for receiving at the secondary processor, from the primary processor via the inter-chip communication bus, the at least one data segment;
- and
- means for loading, by the secondary processor, the at least one data segment directly to the determined at least one location within the system memory.
2 more elements
A multi-processor system comprising:
- a primary processor coupled with a first non-volatile memory, the first non-volatile memory coupled to the primary processor and storing a file system for the primary processor and executable images for the primary processor and secondary processor;
- a secondary processor coupled with a second non-volatile memory, the second non-volatile memory coupled to the secondary processor and storing configuration parameters and file system for the secondary processor;
- and
- an interface communicatively coupling the primary processor and the secondary processor via which an executable software image is received by the secondary processor.
1 more element
A multi-processor system comprising:
- a primary processor coupled with a first non-volatile memory, the first non-volatile memory coupled to the primary processor and storing executable images and file systems for the primary and secondary processors;
- a secondary processor not directly coupled to the first non-volatile memory;
- and
- an interface communicatively coupling the primary processor and the secondary processor via which an executable software image is received by the secondary processor.
1 more element
A method comprising:
- sending, from a memory coupled to a primary processor, an executable software image for a secondary processor, via an interface communicatively coupling the primary processor and secondary processor;
- receiving, at the secondary processor, the executable software image;
- and
- executing, at the secondary processor, the executable software image.
1 more element
Dependencies are inferred from the claim text.