Split path multiply accumulate unit
AssigneeIntel Corporation
InventorsSURESH SRINIVASAN, RAJARAM RAMANARAYANAN, SANU K. MATHEW, RAM K. KRISHNAMURTHY, VASANTHA K. ERRAGUNTLA
Life of this patent
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Abstract
In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed.
Claims20
An apparatus comprising:
- multiply accumulate (MAC) unit to perform a multiply and accumulate operation on first, second and third operands, the MAC unit including:
- an exponent compute datapath to determine a difference based on an exponent portion of the first, second, and third operands, and having a first shifter to shift a mantissa of the third operand by a first amount if the difference is within a threshold range, second shifter to shift the third operand mantissa by a second amount, and a third shifter to shift the third operand mantissa by a third amount, if the difference is outside the threshold range;
- a multiplier datapath including a multiplication tree, wherein the exponent compute datapath is to provide the shifted third operand mantissa to the multiplier datapath if the difference is within the threshold range;
- a compressor to compress an output of the multiplier datapath and the third operand mantissa if the difference is outside the threshold range, wherein the multiplier datapath output is not to be compressed in the compressor if the difference is within the threshold range;
- a first normalizer to normalize the multiplier datapath output if the difference is within the threshold range;
- a second normalizer to normalize the compressor output if the difference is outside the threshold range;
- a computation unit to receive the first and second normalizer outputs and to generate a final value for the multiply and accumulate operation therefrom.
A processor comprising:
- a front end unit to fetch and decode a multiply-accumulate instruction having first, second and third operands associated therewith;
- a renamer coupled to the front end unit to allocate at least one of the first, second and third operands to a register of a register file;
- a multiply-accumulate (MAC) unit coupled to the renamer and having a first path to handle execution of the multiply-accumulate instruction if a difference between at least a portion of the first and second operands and the third operand is less than a threshold value, and a second path to handle execution of the multiply-accumulate instruction if the difference is greater than the threshold value, wherein a portion of the third operand is to be provided to a multiplier of the MAC unit if the difference is less than the threshold value, and otherwise the third operand is to be provided to a compressor of the second path.
A method comprising:
- receiving first, second, and third operands in a multiply accumulate (MAC) unit;
- determining a difference between exponents of the first and second operands, and an exponent of the third operand;
- providing at least a portion of the third operand to a multiplier datapath of the MAC unit for accumulation with intermediate results of a multiplication operation on at least a portion of the first and second operands if the difference is within a threshold range;
- and
- otherwise providing the third operand portion to a compressor for accumulation with a product output by the multiplier datapath.
Dependencies are inferred from the claim text.