Multi-level register file supporting multiple threads

A processor, comprising:

• an instruction fetch unit;
• an issue queue coupled to the instruction fetch unit;
• an execution unit coupled to the issue queue;
• a multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency, each of the first and second level register files including a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads;
• and
• a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file;
• wherein the issue queue, in response to a signal from the mapper, issues the instruction to the execution unit for execution.

A data processing system, comprising:

• a system memory;
• a plurality of processor cores coupled for communication with the system memory, wherein a processor core among the plurality of processor cores includes:
• an instruction fetch unit;
• an issue queue coupled to the instruction fetch unit;
• an execution unit coupled to the issue queue;
• a multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency, each of the first and second level register files including a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads;
• and
• a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file;
• wherein the issue queue, in response to a signal from the mapper, issues the instruction to the execution unit for execution.

A program product, comprising:

• a computer-readable storage medium;
• and
• program code stored on the computer-readable storage medium that, when processed by a computer causes the computer to model processor operation by performing:
• in a simulated processor, holding operands of a plurality of threads in a shared first level register file having a lower access latency and holding operands of the plurality of threads in a shared second level register file having a higher access latency;
• at dispatch of an instruction specifying a source logical register, a mapper in the simulated processor initiating a swap of a first operand associated with the source logical register that is held in the second level register file with a second operand in the first level register file;
• and
• thereafter, issuing the instruction for execution by the simulated processor.