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US 2012/0072699 A1Published application
Logic cell array and bus system
OwnerMartin VORBACH, Frank May +7inventors
InventorsMartin VORBACH, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel
Life of this patent
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Abstract
A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
Claims31
1-37. (canceled)
A data processor on a chip comprising:
- a plurality of data processing cores, each of at least some of the processing cores including:
- at least one arithmetic logic unit that supports at least division and multiplication of at least 32-bit wide data;
- and
- at least 3 registers for storing at least 32-bit wide data;
- a plurality of memory units to buffer at least 32-bit wide data;
- at least one interface unit for providing at least one communication channel between the data processor and external memory;
- and
- a bus system flexibly interconnecting the plurality of processing cores, the plurality of memory units, and the at least one interface;
- wherein:
- the bus system includes a first structure dedicated for data transfer in a first direction and a second structure dedicated for data transfer in a second direction;
- and
- each of at least some of the data processing cores includes a physically dedicated connection to at least one physically assigned one of the plurality of memory units, the assigned one of the plurality of memory units being accessible by another of the data processing cores via a secondary bus path of the bus system.
9 more elements
A data processor on a chip comprising:
- a plurality of data processing cores, each of at least some of the processing cores including:
- at least one arithmetic logic unit that supports at least division and multiplication of at least 32-bit wide data;
- and
- at least 3 registers for storing at least 32-bit wide data;
- a plurality of memory units to buffer at least 32-bit wide data;
- at least one interface unit for providing at least one communication channel between the data processor and external memory;
- and
- a bus system flexibly interconnecting the plurality of processing cores, the plurality of memory units, and the at least one interface;
- wherein:
- the bus system includes a first structure dedicated for data transfer in a first direction and a second structure dedicated for data transfer in a second direction;
- and
- each of at least some of the data processing cores includes a dedicated connection to at least one assigned one of the plurality of memory units each situated such that no other data processing core and no other memory unit is positioned between the respective data processing core and the respective assigned memory unit, the assigned one of the plurality of memory units being accessible by another of the data processing cores via a secondary bus path of the bus system.
9 more elements
Dependencies are inferred from the claim text.