Multi-Ported Memory Controller with Ports Associated with Traffic Classes

An integrated circuit comprising:

• one or more real time (RT) peripherals;
• at least one processor;
• one or more non-real time (NRT) peripherals;
• and
• a memory controller having a plurality of ports, wherein the one or more RT peripherals are coupled to an RT port of the plurality of ports, the at least one processor is coupled to a first NRT port of the plurality of ports, and wherein the one or more NRT peripherals are coupled to a second NRT port of the plurality of ports, and wherein the memory controller is configured to capture memory operations from the plurality of ports and to schedule the memory operations on one or more memory channels to memory, wherein scheduling determinations between memory operations received on different ports are dependent in part on the specific ports on which the memory operations were received.

A method comprising:

• receiving a first memory operation on a real time (RT) port into a memory controller, wherein the first memory operation has a first quality of service (QoS) parameter defined according to a set of RT QoS levels;
• receiving a second memory operation on a non-real time (NRT) port into a memory controller in parallel with the first memory operation, wherein the second memory operation has a second QoS parameter defined according to a set of NRT QoS levels;
• and
• the memory controller scheduling the first memory operation and the second memory operation to access the memory at least in part in response to the first QoS parameter and the second QoS parameter.

An integrated circuit comprising:

• a first source of memory operations;
• a second source of memory operations;
• a first interface to which the first source is coupled;
• a second interface to which the second source is coupled;
• and
• a memory controller having a first port coupled to the first interface and a second port coupled to the second interface, wherein a first protocol on the first interface differs from a second protocol on the second interface, and wherein the memory controller is configured to communicate via the first protocol on the first interface, and wherein the memory controller is configured to communicate via the second protocol on the second interface.