Prefetch address hit prediction to reduce memory access latency

A prefetch unit for provisioning data for anticipated memory prefetches in caching systems, comprising:

• a memory interface that is arranged to receive memory read requests each having an associated address, wherein the associated address points to data stored in a lower-level hierarchical memory;
• an array that includes slots for storing a portion of a predicted address and the prefetched data associated with the predicted address;
• a prefetch FIFO (First In-First Out) counter having a counting system that is arranged to cycle through the slots of the array to allocate each next slot for storing subsequent indications of the address of subsequent cache requests in turn before wrapping around to a first slot of the filter array;
• a prefetch predictor that is arranged to determine a next predicted address in response to a prefetch address stored in a slot of an array and to provision data prefetched in response to the next predicted address and stored in the array;
• and
• a comparator that is arranged to enable the read-out the provisioned data in response to a subsequent memory read request that is received after the next predicted address has been predicted by the prefetch predictor, wherein the subsequent memory read request contains an address that is associated with the next predicted address.