Slot/sub-slot prefetch architecture for multiple memory requestors

A digital system, comprising

• a processor that is arranged to generate demand fetches for data stored in a hierarchical cache system;
• a first cache and a second cache arranged in the hierarchical cache system, wherein the second cache has a second cache line width that is twice as long as a first cache line width, wherein the second cache is at a different hierarchical level than the first cache;
• and
• a prefetch unit that includes a prefetch address generator that is arranged to generate a prefetch address in response to an address associated with a memory read request received from the first or second cache, wherein the prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, wherein each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots wherein each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and wherein one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address.

A multi-stream prefetch unit for generating memory prefetches in caching systems, comprising:

• a memory interface that is arranged to receive memory read requests from a requestor that is one of a first and second cache, wherein the first cache has a cache line length that is less than a cache line length of the second cache, wherein the first cache is at a different hierarchical level than the second cache, and wherein each memory request has an associated address that points to data stored in a memory that is at a lower hierarchical level than the first and second caches;
• a data prefetch unit that is arranged to generate prefetch addresses in response to addresses associated with memory read requests, and that is arranged to store the prefetch addresses in slots of the data prefetch buffer, wherein each slot is arranged to store data that is prefetched in response to the prefetch address stored in the address buffer of the slot, wherein each slot includes a first and second sub-slot wherein each sub-slot includes data buffer that is arranged to store prefetch data having a data-width of the cache line length of the first cache;
• and
• a prefetch unit selector that is arranged to enable the data prefetch unit in response to a determination of whether the received memory read request is requesting data that is not program instruction data.