Variable line size prefetcher for multiple memory requestors
AssigneeTexas Instruments Incorporated
InventorsTimothy D. Anderson, Kai Chirca
Life of this patent
Estimating the term…
Abstract
A prefetch unit generates prefetch addresses in response to an initial received memory read request, an address associated with the initial received memory read request, a line length of the requestor of the initial received memory read request, and a request type width of the initial received memory read request. Prefetch operations are generated using the generated prefetch addresses, wherein each generated prefetch address is stored in a prefetch buffer slot that is selected by a prefetch FIFO (First In First Out) prefetch counter. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.
Claims20
A method for generating memory prefetches in caching systems, comprising:
- receiving an initial memory read request from a requestor that is one of a first level cache and a second level cache wherein the first level cache is at a higher level than the second level cache;
- generating a prefetch addresses in response to the initial received memory read request, an address associated with the initial received memory read request, a line length of the requestor of the initial received memory read request, and a request type width of the initial received memory read request;
- generating prefetch operations using the generated prefetch addresses, wherein each generated prefetch address is stored in a prefetch buffer slot that is selected by a prefetch FIFO (First In First Out) prefetch counter, wherein each slot includes an address buffer for storing one of the generated prefetch addresses and includes a data buffer for storing data that is prefetched in response to the prefetch address stored in the address buffer of the slot, wherein a size of the data buffer is selected in response to the request type width of the initial received memory read request;
- and
- returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.
A digital system, comprising:
- a memory system including a hierarchical cache system for storing and retrieving data;
- a prefetch unit that includes a prefetch address generator that is arranged to generate prefetch addresses in response to addresses associated with memory read requests received from a first or second cache, and that includes prefetch buffer that is arranged to store the prefetch addresses in slots of the prefetch buffer, wherein each slot includes a buffer for storing a prefetch address, a data buffer for storing data that is prefetched using the prefetch address stored in the same slot, and a wherein a size of the data buffer is selected in response to at least one operating parameter of the received memory read request.
A multi-stream prefetch unit for generating memory prefetches in caching systems, comprising:
- a memory interface that is arranged to receive from a memory read requests each having an associated address, wherein the associated address points to data stored in a lower-level hierarchical memory;
- a data prefetch unit that is arranged to generate prefetch addresses in response to addresses associated with memory read requests, and that is arranged to store the prefetch addresses in slots of the data prefetch buffer, wherein each slot includes a buffer for storing a prefetch address and a variable-size buffer for storing data that is prefetched using the prefetch address stored in the same slot;
- a program prefetch unit that is arranged to generate prefetch addresses in response to addresses associated with memory read requests, and that is arranged to store the prefetch addresses in slots of the program prefetch buffer, wherein each slot includes a buffer for storing a prefetch address and a variable-size buffer for storing data that is prefetched using the prefetch address stored in the same slot;
- and
- a prefetch unit selector that is arranged to select the program prefetch unit in response to a determination of whether the received memory read request is requesting program instruction data, that is arranged to select the data prefetch unit in response to a determination of whether the received memory read request is requesting data that is not program instruction data, and to send the received memory read request to the selected one of the program prefetch unit or the data prefetch unit.
Dependencies are inferred from the claim text.