Memory device with user configurable density/performance
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
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Abstract
The memory device is comprised of a memory array having a plurality of memory cells that are organized into memory blocks. Each memory cell is capable of storing a selectable quantity of data bits (e.g., multiple level cells or a single bit per cell). Control circuitry controls the density configuration of read or write operations to the memory blocks in response to a configuration command. In one embodiment, the configuration command is part of the read or write command. In another embodiment, the configuration command is read from a configuration register.
Claims20
A memory device having selectable density configurations, the device comprising:
- a memory array comprising a plurality of memory cells, each memory cell configured to store a selectable quantity of data bits, the memory array organized into memory blocks;
- a configuration register;
- and
- control circuitry, coupled to the memory array, that controls the density configuration in response to a configuration command, wherein each memory block is assigned a plurality of configuration bits of the configuration register such that each memory block is configured to have multiple densities.
A NAND flash memory device having selectable density configurations, the device comprising:
- a memory array comprising a plurality of memory cells that are organized into memory blocks, each memory cell configured to store a selectable quantity of data bits;
- control circuitry, coupled to the memory array, that determines the density configuration for a memory block in response to a configuration bit;
- and
- a configuration register, coupled to the control circuitry, for storing the configuration bit, wherein each memory block is assigned a plurality of density configuration bits.
A semiconductor, non-volatile memory device having a plurality of selectable density configurations, the device comprising:
- a memory array comprising a plurality of memory cells grouped into memory blocks, each memory cell configured to store a selectable quantity of data bits;
- a control bus for receiving density configuration commands that are included in read and write commands;
- and
- control circuitry coupled to the memory array and the control bus and configured to control the density configuration in response to the received density configuration commands and programming of a configuration register, wherein each memory block is assigned a plurality of configuration bits of the configuration register such that each memory block is configured to have multiple densities.
A method for configuring performance of a memory array, organized as memory blocks, in a memory device, the memory device comprising control circuitry coupled to a configuration register, the method comprising:
- loading configuration data into the configuration register;
- and
- setting a performance configuration for at least a subset of the memory array in response to the configuration data, wherein each memory block is configured to have a plurality of density configurations.
A method for configuring performance of a memory array having a plurality of memory blocks, the method comprising:
- receiving configuration data;
- and
- setting a performance configuration for at least a memory block of the memory array in response to the received configuration data, wherein each memory block is configured to be assigned multiple configuration data.
A method for configuring the density of a memory array, organized as memory blocks, the method comprising:
- receiving a command for initiating one of a read or a write operation on a memory block;
- determining if the received command comprises a memory density configuration;
- executing one of a single bit per cell read/write routine or a multilevel cell read/write routine on the memory block at the memory density configuration specified in the command;
- and
- storing the memory density configuration from the command in a configuration register, wherein each memory block is configured to have multiple memory density configurations as indicated by the configuration register.
Dependencies are inferred from the claim text.