Memory system and dram controller

A memory system comprising:

• a nonvolatile memory;
• a DRAM configured to temporarily store transfer data between the nonvolatile memory and a host device;
• and
• a DRAM controller configured to execute an initialization processing of the DRAM and execute an input/output of the transfer data to/from the DRAM in a normal operation after the initialization processing,
• the DRAM controller including:
• a clock generating and switching unit configured to supply a first clock to the DRAM in the normal operation and generate a second clock having a lower speed than the first clock and supply the generated second clock to the DRAM in the initialization processing;
• and
• a DRAM access circuit having a DLL circuit configured to regulate a fetch timing of data output from the DRAM based on the first clock, and fetch, in a fetch timing regulated by the DLL circuit, the data output from the DRAM in a timing based on the second clock in relation to the initialization processing and the transfer data output from the DRAM in a timing based on the first clock in the initialization processing and the normal processing, respectively.