US 2012/0072648 A1 · NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Abstract

A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.

Claims20

Dependent claims

A nonvolatile semiconductor memory device comprising:

a memory cell array having electrically rewritable nonvolatile memory cells arranged therein;
and
a control unit configured to perform control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected one of the memory cells for data write, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage by an amount of a step-up voltage if data write is not completed,
the control unit being configured to, during the write operation, raise a first write pulse voltage with a first gradient, and then raise a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.

1 more element

A nonvolatile semiconductor memory device comprising:

a memory cell array having electrically rewritable nonvolatile memory cells arranged therein;
and
a control unit configured to perform control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected one of the memory cells for data write, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage by an amount of a step-up voltage if data write is not completed,
the control unit being configured to perform voltage control such that, during the write operation, a rise time to reach a first voltage for a first write pulse voltage is longer than that for a second write pulse voltage, the first write pulse voltage including at least a write pulse voltage generated at first, and the second write pulse voltage being generated after the first write pulse voltage.

1 more element

A nonvolatile semiconductor memory device comprising:

a memory cell array having electrically rewritable nonvolatile memory cells arranged therein;
and
a control unit configured to perform control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected one of the memory cells for data write, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage by an amount of a step-up voltage if data write is not completed,
the control unit being configured to perform voltage control such that, during the write operation, a relation of Wp/3≦t is satisfied, where Wp is a pulse width of a first write pulse voltage, and t is a width of a portion of a rise curve of the first write pulse voltage until the first write pulse voltage reaches a value, the first write pulse voltage including at least a write pulse voltage generated at first.

1 more element

Dependencies are inferred from the claim text.

Nonvolatile semiconductor memory device

Life of this patent

Nonvolatile semiconductor memory device

Life of this patent

Abstract

Claims20