Different types of memory integrated in one chip by using a novel protocol
AssigneeAplus Flash Technology, Inc.
InventorsPeter Wung Lee, Fu-Chang Hsu
Life of this patent
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Abstract
A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I2C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.
Claims17
A memory chip, comprising:
- a) a plurality of memories,
- b) a plurality of serial parallel protocols;
- c) a limited number of electrical pins;
- d) a hardware serial interface;
- e) each memory of said plurality of memories formed of a different memory type and integrated together into a same semiconductor device by the use of a unified manufacturing process;
- f) said hardware serial interface provides a bidirectional function to conserve a usage of said electrical pins and to transfer commands, addresses and data into said device and data out of the device, wherein the serial-parallel protocols control the read, write and transfer of data in and out of the device, including write-while-write and read-while-write operations in the plurality of memories, wherein a state of a serial clock (SCK) signal and an input signal of a serial input output (SIO) determines memory operations.
A method for forming a multi-structured memory cells into one integrated circuit chip, comprising:
- a) integrating together into a single memory chip a plurality of types of dissimilar memory cell using a unified manufacturing process to form a plurality of dissimilar memories;
- b) forming a serial interface;
- and
- c) controlling operation of said dissimilar memories with a plurality of serial parallel protocols, wherein said protocols applied through a signal input to said serial interface (SIO), wherein said protocols operate in conjunction with a serial clock (SCK) to control read and write of said memory cells and transfer data in and out of said memory chip.
A method of acknowledgement polling for a selected memory, comprising:
- a) issuing a command code to perform a write operation;
- b) initiating a write cycle from a host device;
- c) sending a start condition;
- d) setting memory select code;
- e) setting expandable memory code;
- f) setting suspend-resume code:
- g) sending a write command control byte;
- and
- h) if acknowledgement of completed write operation received, then next operation, else return to step c).
13:
- The method of claim 11, wherein said acknowledgement is requested by a host device to determine whether the write operation on a selected memory is complete.
A method to status register using SPI, SDI and SQI protocol, comprising:
- a) initiating a write cycle for a memory by an internal state machine with a predetermined timer;
- b) sending a start condition by a host device;
- c) setting memory select code and interface select code;
- d) setting expandable memory register code and suspend-resume code;
- e) sending read status register (SR) command code;
- f) receiving SR code by the host device;
- and
- g) continuing to the next operation.
Dependencies are inferred from the claim text.