Nonvolatile semiconductor memory

A nonvolatile semiconductor memory comprising:

• a memory cell array with a block including word lines, and each word line connected to memory cells;
• a controller which controls a data erase of the memory cells in the block;
• and
• a verify circuit which verifies whether or not the data erase is completed,
• wherein the controller comprises:
• being executed a verification by the verify circuit using an erase verify potential as a lower limit of a threshold distribution of an erase state after being executed a first block erase,
• being executed a second block erase continuously when the number of memory cells having a threshold voltage lower than the erase verify potential by the verification is n (n is a natural number) or less, and
• being executed a page erase continuously when the number of memory cells having a threshold voltage lower than the erase verify potential by the verification is more than n.