Single step processing of memory mapped accesses in a hypervisor

Abstract

Trapping and/or processing of read/write accesses to hardware devices represented to the host through a memory mapped space may be performed without knowledge of the processor's instruction set or semantics of the processor's instructions. A single step routine may be executed to recognize page faults occurring from read/write accesses to emulated memory pages and causing the guest to retry the operation on a single step buffer. The hypervisor may perform post-operation processing on the single step buffer after the guest retries and completes the read or write access. For example, on a read request, the single step routine may place the guest value in the single step buffer for reading by the guest on a retry operation. On a write request, the single step routine may direct the guest to retry the write operation into the single step buffer. After the retry operation the single step routine may read the guest value from the single step buffer and place the guest value in a register of an appropriate emulated system.

Dependencies are inferred from the claim text.