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US 2012/0072632 A1Published application
Deterministic and non-Deterministic Execution in One Processor
OwnerPaul Kimelmaninventor
Life of this patent
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Abstract
An application in a data processing system may automatically select when it needs determinism and when it does not. The ability to have the system automatically select when to use each allows optimum system performance while maintaining hard real-time requirements when needed.
Claims19
A method for operating a digital system having a processor and a memory configured to store instructions for an application, the method comprising:
- determining when a cache should be enabled and disabled during execution of the instructions by the processor;
- automatically disabling cache operation in response to each determination that the cache should be disabled;
- and
- automatically enabling cache operation in response to each determination that the cache should be enabled.
1 more element
A method for operating a digital system having a processor and a memory configured to store instructions for an application, the method comprising:
- determining when a cache should be enabled and disabled during execution of the instructions by the processor;
- programmatically disabling cache operation each time it is determined the cache should be disabled, wherein disabling cache operation comprises reconfiguring at least of a portion of the cache to operate as a read buffer;
- and
- programmatically enabling cache operation each time it is determined the cache should be enabled, wherein enabling cache operation comprises reconfiguring the read buffer to operate again as a cache.
1 more element
A system comprising an integrated circuit, wherein the integrated circuit comprises:
- a memory module operable to store instructions;
- at least one processor coupled to execute instructions stored in the memory module;
- a cache coupled to the processor and to the memory module;
- state detection logic coupled to the processor, wherein the state detection logic is configured to determine when the processor is executing in a real-time state;
- and
- wherein the cache is configured to be disabled in response to a control signal from the state detection logic while the processor is executing in the real-time state.
3 more elements
Dependencies are inferred from the claim text.