Memory system having high data transfer efficiency and host controller

A host controller comprising:

• a register set configured to control command issue to a device;
• and
• a direct memory access (DMA) unit configured to access a system memory,
• wherein the host controller controls data transfer between the system memory and the device,
• the host controller loads a first descriptor stored in the system memory, and including a set of a plurality of pointers indicating a plurality of second descriptors, a third descriptor forming each of the plurality of second descriptors, and including a command number, a command operation mode, and an argument as information necessary to issue a command to the device, and a block length and the number of blocks as information necessary for data transfer, and a fourth descriptor forming each of the plurality of second descriptors, and including information indicating addresses and sizes of a plurality of data arranged in the system memory, and
• the DMA unit sets, in the register set, contents of the third descriptor forming the second descriptor, from a head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with contents of the fourth descriptor.

A DMA transfer control method comprising:

• loading, from a memory, a second descriptor pointer described first among a plurality of second descriptor pointers described in a first descriptor;
• loading, from the memory, a second descriptor indicated by the loaded second descriptor pointer;
• loading, from the memory, a third descriptor described at a head of the second descriptor, writing contents of the third descriptor in a register, and issuing a command;
• loading a fourth descriptor from the memory, loading data indicated by an address described in the fourth descriptor, and transferring the data between a system memory and a buffer;
• and
• repeating the above-mentioned operation, and generating an interrupt when all data have been transferred.