Stress-adjusting method of mos device
AssigneeUnited Microelectronics Corp.
InventorsJei-Ming CHEN, Szu-Hao LAI
Life of this patent
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Abstract
A stress-adjusting method for use in a manufacturing system of a MOS device is provided. At first, a first stress layer is formed onto a substrate wherein at least two MOSFETs are previously formed on the substrate. The first stress layer overlies an inter-gate region between two adjacent gate regions of the MOSFETs and overlies the two adjacent gate regions. Then, the first stress layer in the inter-gate region is thinned. A second stress layer is further formed onto the substrate to overlie the thinned first stress layer in the inter-gate region to provide the resulting MOS device with satisfactory stress.
Claims18
A stress-adjusting method for use in a manufacturing system of a MOS device, comprising:
- forming a first stress layer onto a substrate with at least two MOSFETs formed thereon, the first stress layer overlying at least a gate region of the MOSFETs and an inter-gate region between two adjacent gate regions of the MOSFETs;
- thinning the first stress layer in the inter-gate region with a dry etching process to obtain a thinned first stress layer;
- and
- forming a second stress layer onto the substrate, overlying the thinned first stress layer in the inter-gate region.
(canceled)
A Stress Memorization Technique (SMT) process for use in a manufacturing system of a MOS device, comprising:
- forming a first stress layer onto a substrate with at least two MOSFETs formed thereon, the first stress layer overlying a gate region and an inter-gate region of the MOSFETs;
- thinning the first stress layer with a dry etching process to obtain a thinned first stress layer;
- forming a second stress layer onto the substrate, overlying the thinned first stress layer;
- annealing the substrate after the second stress layer is formed;
- and
- removing the thinned first stress layer and the second stress layer.
(canceled)
(canceled)
Dependencies are inferred from the claim text.