Passivation of integrated circuits containing ferroelectric capacitors and hydrogen barriers

A process of forming an integrated circuit, comprising:

• providing a partially processed integrated circuit having an FeCap region, a buffer region, and a logic region with an overlying first hydrogen barrier layer;
• forming a photoresist pattern that is closed over said FeCap region and over said buffer region but is open over a portion of said logic region;
• and
• etching said first hydrogen barrier layer from said portion of said logic region.