Semiconductor device having decreased contact resistance
AssigneeGlobalfoundries Inc.
InventorsZhonghai SHI, David WU, Mark MICHAEL, Donna Michael
Life of this patent
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Abstract
Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.
Claims12
A method for fabricating a semiconductor device comprising the steps of:
- forming a semiconductor device structure;
- depositing dielectric material to form an interlayer dielectric (ILD) layer over the semiconductor device structure;
- selectively etching an opening through the ILD layer, wherein the opening includes a first portion having a first depth and a second portion having a second depth;
- and
- filling the opening with conductive material to form a contact, wherein the contact is electrically and physically coupled to the semiconductor structure at a sidewall portion thereof in the first portion of the opening and is electrically and physically coupled to the semiconductor structure at a surface portion thereof in the second portion of the opening.
A method for fabricating a semiconductor device comprising the steps of:
- forming a semiconductor transistor structure;
- depositing dielectric material to form an interlayer dielectric (ILD) layer over the semiconductor transistor structure;
- selectively etching an opening through the ILD layer, wherein the opening includes a first portion having a first depth and a second portion having a second depth;
- and
- filling the opening with conductive material to form a contact, wherein the contact is electrically and physically coupled to the semiconductor transistor structure at a sidewall portion thereof in the first portion of the opening and is electrically and physically coupled to the semiconductor transistor structure at a surface portion thereof in the second portion of the opening;
- wherein:
- the second portion includes one or more subportions;
- the first portion includes one or more finger portions, each of the plurality of subportions of the second portion separated from another one of the plurality of subportions by one of the one or more finger portions;
- the step of filling the opening with conductive material to form the contact comprises the step of filling the opening with conductive material to form a contact;
- and
- the contact is electrically and physically coupled to the semiconductor structure at one or more sidewall portions thereof in each of the one or more finger portions of the opening and is electrically and physically coupled to the semiconductor structure at a surface portion thereof in each of the one or more subportions of the second portion of the opening.
A method for fabricating a semiconductor device comprising the steps of:
- providing a substrate;
- etching a trench in the substrate;
- filling the trench with a selectively etchable material;
- forming a semiconductor device structure at a location the substrate adjoining the trench;
- depositing dielectric material to form an interlayer dielectric (ILD) layer over the semiconductor device structure;
- selectively etching an opening through the ILD layer, wherein the opening includes a first portion having a first depth and a second portion having a second depth, and wherein the step of selectively etching the opening through the ILD layer comprises the step of selectively etching the first portion of the opening through the ILD layer and the selectively etchable material in the trench to expose the sidewall portion of the semiconductor device structure;
- and
- filling the opening with conductive material to form a contact, wherein the contact is electrically and physically coupled to the semiconductor structure at a sidewall portion thereof in the first portion of the opening and is electrically and physically coupled to the semiconductor structure at a surface portion thereof in the second portion of the opening.
Dependencies are inferred from the claim text.