Semiconductor device manufacturing method
AssigneeElpida Memory, Inc.
InventorHirotaka KOBAYASHI
Life of this patent
Estimating the term…
Abstract
A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved.
Claims4
A manufacturing method of a semiconductor device comprising:
- forming a wiring layer including a plurality of wiring lines, the plurality of wiring lines being arranged in a first direction, each of the plurality of wiring lines being extending in a second direction different from the first direction, the surface of each of which is covered with an insulation protecting film;
- forming a first interlayer insulation film to cover the wiring layer;
- forming a plurality of dummy insulation films above the first interlayer insulation film, in a same layout as that of the plurality of wiring lines, such that each of dummy insulation films is aligned with a corresponding one of the plurality of wiring lines;
- forming a second interlayer insulation film to cover the plurality of dummy insulation films and the first interlayer insulation film;
- forming a slit groove in the second interlayer insulation film continuously extending in the first direction to expose the plurality of wiring lines;
- forming a plurality of via holes passing through the first and second interlayer insulation films from the slit groove, in a self-aligned manner with the plurality of wiring lines, the insulation protecting film, and the plurality of dummy insulation films;
- and
- forming a conductive layer in the plurality of via holes and the slit groove, and on the second interlayer insulation film;
- removing the conductive layer on the second interlayer insulation film and in the slit groove, and further a portion of the second interlayer insulation film to form a plurality of via plugs isolated from each other within a corresponding one of the via holes.
A manufacturing method of a semiconductor device comprising:
- forming a wiring layer including a plurality of wiring lines, the plurality of wiring lines being arranged in a first direction, each of the plurality of wiring lines being extending in a second direction perpendicular to the first direction, the surface of each of which is covered with an insulation protecting film;
- forming a first interlayer insulation film to cover the wiring layer;
- forming a plurality of dummy insulation films above the first interlayer insulation film, in a same layout as that of the plurality of wiring lines, such that each of dummy insulation films is aligned with a corresponding one of the plurality of wiring lines;
- forming a second interlayer insulation film to cover the plurality of dummy insulation films and the first interlayer insulation film;
- forming a slit groove in the second interlayer insulation film continuously extending in the first direction to expose the plurality of wiring lines;
- forming a plurality of via holes passing through the first and second interlayer insulation films from the slit groove, in a self-aligned manner with the plurality of wiring lines, the insulation protecting film, and the plurality of dummy insulation films;
- and
- forming a plurality of via plugs within the via hole holes, the via plugs being isolated from each other.
Dependencies are inferred from the claim text.