Methods of Forming Gate Structure and Methods of Manufacturing Semiconductor Device Including the Same
AssigneeSamsung Electronics Co., Ltd.
InventorsHa-Jin Lim, Moon-Han Park, Min-Woo Song, Jin-Ho Do, Weon-Hong Kim, Moon-Kyun Song, Dae-Kwon Joo
Life of this patent
Estimating the term…
Abstract
A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented.
Claims20
A method of forming a gate structure comprising:
- forming a gate insulating layer on a substrate;
- forming a metal layer on the gate insulating layer;
- forming an amorphous silicon layer on the metal layer by a physical vapor deposition (PVD) process;
- and
- forming an impurity doped polysilicon layer on the amorphous silicon layer.
A method of manufacturing a semiconductor device comprising:
- forming a gate insulating layer on a substrate;
- forming a metal layer on the gate insulating layer;
- forming an amorphous silicon layer on the metal layer through a physical vapor deposition (PVD) process;
- forming an impurity doped polysilicon layer on the amorphous silicon layer;
- annealing the semiconductor device to activate impurities included in the impurity doped polysilicon layer and to crystallize the amorphous silicon layer to form a crystalline silicon layer;
- and
- patterning the impurity doped polysilicon layer, the crystalline silicon layer, the metal layer, and the gate insulating layer one by one to form a gate structure including a gate insulating layer pattern, a metal layer pattern, a crystalline silicon layer pattern and an impurity doped polysilicon layer pattern.
A method of forming a gate structure, comprising:
- forming a gate insulating layer on a substrate;
- forming a metal layer on the gate insulating layer;
- forming a crystalline silicon layer on the metal layer;
- and
- forming an impurity doped polysilicon layer on the crystalline silicon layer;
- wherein the crystalline silicon layer has a larger grain size than the impurity doped polysilicon layer.
Dependencies are inferred from the claim text.