Non-uniformity reduction in semiconductor planarization
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsNeng-Kuo Chen, Jeff J. Xu
Life of this patent
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Abstract
Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.
Claims20
A method, comprising:
- providing a substrate;
- forming a first layer over the substrate;
- forming a second layer over the first layer, the first and second layers having different material compositions;
- forming a third layer over the second layer;
- performing a polishing process on the third layer until the third layer is substantially removed;
- and
- performing an etch back process to remove the second layer and a portion of the first layer, wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.
A method, comprising:
- providing a wafer having a first region and a second region, the first and second regions having different pattern densities;
- forming a first layer over the first and second regions of the wafer;
- forming a second layer on the first layer;
- forming a third layer on the second layer;
- polishing away the third layer until portions of the second layer overlying both the first and second regions are reached, the second layer serving as a polishing-stop layer;
- and
- etching back the second layer and a portion of the first layer, wherein the first and second layers have substantially identical etching rates.
A method, comprising:
- providing a substrate, wherein the substrate includes portions having different pattern densities;
- forming a first layer over the portions of the substrate having the different pattern densities, wherein the first layer includes a material selected from the group consisting of:
- a polysilicon material and an inter-layer dielectric (ILD) material;
- forming a second layer over the first layer;
- forming a third layer over the second layer, wherein the second and third layers have substantially different polishing rates;
- performing a chemical-mechanical-polishing (CMP) process on the third layer, wherein the second layer functions as a stop layer for the CMP process;
- and
- thereafter performing an etch back process to remove the second layer and a portion of the first layer, wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.
Dependencies are inferred from the claim text.