Methods of Manufacturing Three Dimensional Semiconductor Devices
OwnerHyu-Jung Kim, Sang-Yong Park +3inventors
InventorsHyu-Jung Kim, Sang-Yong Park, JongHeun Lim, Kyunghyun Kim, ChangSup Mun
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Abstract
Provided are methods of manufacturing a three dimensional semiconductor device. The method includes providing a substrate including a cell array region and a peripheral circuit region, forming a peripheral structure on the peripheral circuit region, forming a cell structure being thicker than the peripheral structure in the cell array region, forming an interlayer dielectric to cover the peripheral structure and the cell structure, forming a polishing stop layer on the interlayer dielectric, and planarizing the interlayer dielectric using the polishing stop layer as a planarization stop.
Claims25
A method of manufacturing a semiconductor device, comprising:
- providing a substrate including a cell array region and a peripheral circuit region;
- forming a peripheral structure including peripheral circuits in the peripheral circuit region and outside the cell array region;
- forming a cell structure including first and second layers alternatingly stacked on the substrate in the cell array region, the cell structure having a greater height than the peripheral structure;
- forming an interlayer dielectric on the peripheral structure and the cell structure;
- forming a polishing stop layer on the interlayer dielectric in the peripheral circuit region and the cell array region;
- and
- planarizing the interlayer dielectric using a portion of the polishing stop layer disposed on the peripheral circuit region as a planarization stop pattern.
A method of manufacturing a semiconductor device, comprising:
- providing a substrate including a cell array region and a peripheral circuit region;
- forming a stacked layer structure including first and second layers alternatingly stacked on the substrate, the stacked layer structure including a contact portion interposed between the cell array region and the peripheral circuit region and having a stepwise structure;
- forming penetrating structures in the stacked layer structure, each of the penetrating structure including a semiconductor pattern penetrating the stacked layer structure;
- forming an interlayer dielectric having a height difference between the cell array region and the peripheral circuit region on the substrate provided with the stacked layer structure;
- forming a polishing stop layer on the interlayer dielectric;
- and
- planarizing the interlayer dielectric to form an interlayer insulating pattern on the peripheral circuit region and the contact portion of the stacked layer structure, wherein planarizing the interlayer dielectric is performed using a portion of the polishing stop layer disposed on the peripheral circuit region and top surfaces of the penetrating structures as a planarization stop.
A method of manufacturing a semiconductor device, comprising:
- providing a substrate including a cell array region;
- a peripheral circuit region, and a contact region interposed between the cell array region and the peripheral circuit region;
- forming a peripheral structure including peripheral circuits on the peripheral circuit region;
- forming a stacked layer structure including first and second layers alternatingly stacked on the cell array region, the stacked layer structure being thicker than the peripheral structure and comprising a stepwise shaped portion disposed on the contact region;
- forming an interlayer dielectric on the peripheral structure and the stacked layer structure;
- forming a polishing stop pattern on the interlayer dielectric, the polishing stop pattern extending from the peripheral circuit region to the contact region and disposed over at least a portion of one of the first layers in the contact region;
- and
- planarizing the interlayer dielectric using the polishing stop pattern as a planarization stop.
A method of manufacturing a semiconductor device, comprising:
- providing a substrate including a cell array region and a peripheral circuit region;
- forming a peripheral structure in the peripheral circuit region;
- forming a cell structure in the cell array region of the substrate, the cell structure having a greater height than the peripheral structure;
- forming a dielectric layer on the peripheral structure and the cell structure;
- forming a polishing stop pattern on the dielectric layer over the peripheral structure, wherein the cell array region is free of the polishing stop pattern;
- and
- planarizing the dielectric layer using the polishing stop pattern as a planarization stop.
Dependencies are inferred from the claim text.