Chip packaging method and structure thereof

A chip packaging method, comprising the following steps:

• (A) providing a chip, a plurality of bonding pads being provided on an upper surface thereof;
• (B) connecting out a plurality of metal wires via bonding, in which a middle part of each of the plurality of metal wires is bent to be higher than a predetermined height, and two ends of each of the plurality of metal wires are respectively electrically connected to two of the plurality of bonding pads;
• (C) packing a molding layer on the chip to cover at least a part of the plurality of metal wires, the molding layer being higher than the predetermined height;
• (D) slicing the molding layer from the place of the predetermined height and cutting out the plurality of metal wires to expose two upper breakpoints of each of the plurality of metal wires;
• and
• (E) attaching a substrate, disposed in advance with a plurality of circuit contacts, onto the molding layer, wherein the plurality of circuit contacts are correspondingly electrically coupled to the upper breakpoints of the plurality of metal wires, respectively.