Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis
AssigneeIntel Corporation
InventorsValery M. DuBin, Florian Gstrein, Gordon D. Holt, Brandon Barnett
Life of this patent
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AssigneeIntel Corporation
InventorsValery M. DuBin, Florian Gstrein, Gordon D. Holt, Brandon Barnett
Estimating the term…
A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
1-30. (canceled)
A method for carrying out a chemical reaction on a plurality of dies on a wafer, the die comprising an electrode to generate a deprotecting reagent, a working electrode and a confinement electrode, wherein the method comprises:
A method of manufacturing a plurality of dies, comprising:
57-77. (canceled)
Dependencies are inferred from the claim text.