Cryptographic apparatus and memory system

A memory system comprising:

• a cryptographic apparatus comprising:
• a plurality of cryptographic cores each of which includes a flag storage unit that stores therein a CipherText Stealing (CTS) flag indicating whether an encryption that utilizes CTS is to be performed and each of which performs, when the CTS flag thereof is turned on, an encryption using a symmetric key cipher algorithm that utilizes CTS, while using a symmetric key;
• an assigning unit that, when having received an input of a CTS signal indicating that second input data that is input immediately after first input data having a block length is shorter than the block length, assigns the first input data to one of the plurality of cryptographic cores and turns on the CTS flag of the one of the cryptographic cores to which the first input data is assigned;
• a concatenating unit that generates concatenated data by concatenating operation data generated during encrypting the first input data at the one of the cryptographic cores and the second input data;
• and
• an output controlling unit that controls outputting the concatenated data to the one of the cryptographic cores, controls outputting first encrypted data obtained by encrypting the concatenated data at the one of the cryptographic cores, and controls outputting second encrypted data obtained by encrypting the first input data at the one of the cryptographic cores, and turns off the CTS flag of the one of the cryptographic cores;
• and
• a memory that stores therein encrypted data that is output from the cryptographic apparatus.