Frequency Synchronization Using Clock Recovery Loop with Adaptive Packet Filtering

A method for use in a communication device, the communication device being operative as a slave device relative to another communication device that is operative as a master device, the method comprising the steps of:

• receiving packets from the master device;
• generating an estimate of phase error between a master clock of the master device and a slave clock of the slave device;
• and
• controlling the slave clock based on the phase error estimate to synchronize the slave clock with the master clock;
• wherein the generating step comprises generating a plurality of different estimates of master clock phase with each such master clock phase estimate being based on at least a subset of the packets received from the master device, and adaptively selecting at least a particular one of the master clock phase estimates for use in generating the phase error estimate.

A communication system, comprising:

• at least first and second communication devices configured to communicate with one another over a packet network;
• a first one of the communication devices being operative as a slave device relative to another one of the communication devices operative as a master device;
• the first communication device comprising a clock recovery loop having a phase error estimator;
• the clock recovery loop being configured to control a slave clock of the slave device responsive to a phase error estimate generated by the phase error estimator so as to synchronize the slave clock with a master clock of the master device;
• the phase error estimator comprising a plurality of filters each configured to generate a different estimate of master clock phase using at least a subset of a plurality of packets received from the master device, and control logic for adaptively selecting at least a particular one of the plurality of filters for use in generating the phase error estimate to be processed in the clock recovery loop.