Data processing apparatus and method

A method of mapping input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the method comprising

• reading-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals,
• reading-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals,
• generating the set of addresses, an address being generated for each of the input symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the generating the set of addresses comprising
• using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial,
• using a permutation circuit operable to receive the content of the shift register stages to permute the bits present in the register stages in accordance with a permutation order to form an address, and
• re-generating an address when a generated address exceeds a predetermined maximum valid address, characterised in that
• the predetermined maximum valid address is approximately sixteen thousand,
• the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of Ri′[12]=Ri-1′[0]⊕ Ri-1′[1]⊕ Ri-1′[4]⊕ Ri-1′[5]⊕ Ri-1′[9]⊕ Ri-1′[11], and the permutation order forms, with an additional bit, a fourteen bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage Ri′[17] in accordance with a code defined by the table:
• R′i bit positions
• 12
• 11
• 10
• 9
• 8
• 7
• 6
• 5
• 4
• 3
• 2
• 1
• 0
• Ri bit
• 8
• 4
• 3
• 2
• 0
• 11
• 1
• 5
• 12
• 10
• 6
• 7
• 9
• positions

A method of transmitting data symbols via a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the method comprising

• receiving a predetermined number of data symbols for mapping onto the predetermined number of sub-carrier signals,
• reading-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals,
• reading-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals,
• generating the set of addresses, an address being generated for each of the input symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the generating the set of addresses comprising
• using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial,
• using a permutation circuit operable to receive the content of the shift register stages to permute the bits present in the register stages in accordance with a permutation order to form an address, and
• re-generating an address when a generated address exceeds a predetermined maximum valid address, characterised in that
• the predetermined maximum valid address is approximately sixteen thousand,
• the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of Ri′[12]=Ri-1′[0]⊕ Ri-1′[1]⊕ Ri-1′[4]⊕ Ri-1′[5]⊕ Ri-1′[9]⊕ Ri-1′[11], and the permutation order forms, with an additional bit, a fourteen bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage Ri′[n] in accordance with a code defined by the table:
• R′i bit positions
• 12
• 11
• 10
• 9
• 8
• 7
• 6
• 5
• 4
• 3
• 2
• 1
• 0
• Ri bit
• 8
• 4
• 3
• 2
• 0
• 11
• 1
• 5
• 12
• 10
• 6
• 7
• 9
• positions

An address generator for use with transmission of data symbols interleaved onto sub-carriers of an Orthogonal Frequency Division Multiplexed symbol, the address generator being operable to generate a set of addresses, each address being generated for each of the data symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the address generator comprising

• a linear feedback shift register including a predetermined number of register stages and being operable to generate a pseudo-random bit sequence in accordance with a generator polynomial,
• a permutation circuit operable to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address, and
• a control unit operable in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, characterised in that
• the predetermined maximum valid address is approximately sixteen thousand,
• the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of Ri′[12] Ri-1′[0]⊕ Ri-1′[1]⊕ Ri-1′[4]⊕ Ri-1′[5]⊕ Ri-1′[9]⊕ Ri-1′[11], and the permutation order forms, with an additional bit, a fourteen bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage Ri′[n] in accordance with the table:
• R′i bit positions
• 12
• 11
• 10
• 9
• 8
• 7
• 6
• 5
• 4
• 3
• 2
• 1
• 0
• Ri bit
• 8
• 4
• 3
• 2
• 0
• 11
• 1
• 5
• 12
• 10
• 6
• 7
• 9
• positions