Digital phase detector and digital phase-locked loop

A digital phase detector comprising:

• an L-phase (L is an integer of at least 2) ring oscillator configured to utilize a reference signal as a trigger;
• a sampler group configured to include a first sampler samples a first signal of N-phase input signals (N is a divisor of L) in accordance with a signal included in L-phase oscillation signals from the ring oscillator and having a most leading phase and a second sampler samples a second signal of N-phase input signals lagging behind the first signal by 2π/N, in accordance with a signal included in the L-phase oscillation signals and having a second most leading phase;
• and
• a detection circuit configured to detect a time difference between an edge of the reference signal and an edge of the first signal based on sampled signals from the sampler group to convert the time difference into a phase difference.

A digital phase detector comprising:

• a first time-to-digital converter configured to quantize a time difference between an edge of a reference signal and an edge of a first signal of N-phase input signals (N is an integer of at least 2) by a first time resolution corresponding to a time difference between adjacent phases of the N-phase input signals to obtain a first quantized value;
• and
• a second time-to-digital converter configured to quantize a time difference between the edge of the reference signal and an edge of a second signal of the N-phase input signals lagging behind the first signal in phase by 2π·K/N (K is an integer of at least 0 and less than M and M is an integral multiple of N) by a second time resolution smaller than the time difference between the adjacent phases of the N-phase input signals to obtain a second quantized value, and
• wherein the second time-to-digital converter comprises:
• a chain of delay devices configured to include M-stage delay devices annularly connected together and to receive the reference signal through (K+1)th stage so that the reference signal is delayed at each stage;
• a first sampler group configured to include a first sampler samples the second signal in accordance with an output signal from the (K+1)th stage of the chain of delay devices and a second sampler samples a third signal of N-phase input signals lagging behind the second signal in phase by 2π/N in accordance with an output signals from a stage following the (K+1)th stage of the chain of delay devices;
• and
• a detection circuit configured to detect the time difference between the edge of the reference signal and the edge of the second signal based on sampled signals from the first sampler group and to obtain the second quantized value.