Implementing exchange of failing lane information for fault-tolerant communication links

A circuit for implementing exchange of failing lane information for fault-tolerant communication links comprising:

• an ordered set used for lane and link training including a lane mask field;
• a transmitter and a receiver exchanging ordered sets during lane and link training to establish synchronization between said transmitter and said receiver;
• said transmitter and said receiver exchanging said ordered set with a plurality of bits of lane mask information included in predefined bytes of the lane mask field in a link training step;
• and
• said transmitter and said receiver responsive to receiving the ordered set with the plurality of bits of lane mask information, reconfiguring the transmitter lanes to align with the received lane mask information.

A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

• a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing exchange of failing lane information for fault-tolerant communication links, said circuit comprising:
• an ordered set used for lane and link training including a lane mask field;
• a transmitter and a receiver exchanging ordered sets during lane and link training to establish synchronization between said transmitter and said receiver;
• said transmitter and said receiver exchanging said ordered set with a plurality of bits of lane mask information included in predefined bytes of the lane mask field in a link training step;
• and
• said transmitter and said receiver responsive to receiving the ordered set with the plurality of bits of lane mask information, reconfiguring the transmitter lanes to align with the received lane mask information, the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.