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US 2012/0069691 A1Published application
Block repair scheme
AssigneeMicron Technology, Inc.
InventorsTakumi Nasu, Takuya Nakanishi
Life of this patent
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Abstract
Systems, memory arrays and methods (e.g., methods of block repair) are provided. One such system includes a memory array including a memory bank including a plurality of sections, wherein each of the plurality of sections includes at least one redundant row. Further embodiments provide for mapping non-redundant rows associated with a section associated with a block failure to distributed redundant rows.
Claims19
A memory array comprising:
- a memory bank comprising a plurality of sections, wherein each of the plurality of sections comprises a plurality of blocks, wherein a first one of the plurality of sections comprises redundant rows, and wherein the number of redundant rows is equal to or greater than the number of non-redundant rows comprised in a second section of the memory array.
A method, comprising:
- mapping non-redundant rows associated with a block failure of a section comprising a plurality of blocks to distributed redundant rows, wherein the distributed redundant rows comprise two or more sections of a memory bank, wherein each of the two or more sections comprise at least one redundant row.
A system, comprising:
- a fuse block, wherein the fuse block is configured to map all non-redundant rows of a bad section of a memory bank to distributed redundant rows, wherein the distributed redundant rows comprise a first row in a first section comprising a first plurality of blocks and a second row in a second section comprising a second plurality of blocks.
Dependencies are inferred from the claim text.