Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device

A controller for a memory device, comprising a control circuit that is configured to:

• set synchronous mode information into the memory device, the synchronous selection mode information comprising a selected one of selection and non-selection modes,
• set edge specifying information into the memory device, the edge specifying information comprising a selected one of first and second states,
• set latency information into the memory device, and
• issue a data read commend to the memory device, the data read command causing the memory device
• to return, after a first period responsive to the latency information has been elapsed, to the controller a first data strobe signal with a first data signal when the selection mode is set,
• to return, after a second period of time responsive to the latency information and the first state has been elapsed, to the controller a second data strobe signal with a second data signal when the non-selection mode and the first state are set, and
• to return, after a third period of time responsive to the latency information and the second state has been elapsed, to the controller a third data strobe signal with a third data signal when the non-selection mode and the second state are set,
• the first data strobe signal being synchronous in phase with a system clock signal, each of the second and third data strobe signals being asynchronous in phase with the system clock signal, and the second and third periods of time being different from each other.