Latch timing adjustment device and memory access system using the same

A latch timing adjustment device configured to adjust latch timing of a data signal output from a memory, the device comprising:

• a first variable delay section configured to delay a strobe signal output from the memory by a first variable delay amount;
• a second variable delay section configured to delay the strobe signal by a second variable delay amount;
• a third variable delay section configured to delay the strobe signal by a third variable delay amount;
• a first data latch section configured to latch the data signal in response to an output of the first variable delay section;
• a second data latch section configured to latch the data signal in response to an output of the second variable delay section;
• a third data latch section configured to latch the data signal in response to an output of the third variable delay section;
• a comparison section configured to perform first comparison between an output of the first data latch section and an output of the second data latch section and second comparison between the output of the second data latch section and an output of the third data latch section;
• and
• a delay adjustment section configured to adjust the first variable delay amount if the result of the first comparison indicates a non-match, adjust the third variable delay amount if the result of the second comparison indicates a non-match, and adjust the second variable delay amount based on the first and third variable delay amounts adjusted.