Semiconductor integrated circuit
AssigneeKabushiki Kaisha Toshiba
InventorsToshiaki Douzaka, Toshiyuki Kouchi, Atsushi Nakayama
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Abstract
According to one embodiment, a semiconductor integrated circuit includes a memory cell array includes data storage units which are arranged at intersections of word lines and bit lines and hold data, a reversing circuit which logically reverses held data stored in the data storage units, and a flag bit column which stores, for each row, a flag for identifying presence/absence of logic reversal of data stored in the data storage units.
Claims20
A semiconductor integrated circuit comprising a memory cell array comprising data storage units which are arranged at intersections of word lines and bit lines and hold data, a reversing circuit which logically reverses held data stored in the data storage units, and a flag bit column which stores, for each row, a flag for identifying presence/absence of logic reversal of data stored in the data storage units.
A semiconductor integrated circuit comprising:
- a memory cell array comprising memory cell units including data storage units which are arranged at intersections of word lines and bit lines and hold data, and a flag bit column which stores, for each row, a flag for identifying presence/absence of logic reversal of data stored in the memory cell units;
- and
- a column decoder comprising a reversing circuit which logically reverses held data stored in the data storage units, and a precharge signal generator which, in a data reverse mode, applies a precharge voltage to a bit line to be selected, and generates a control signal for assisting reverse data write.
A semiconductor integrated circuit comprising:
- data storage units which are arranged at intersections of word lines and bit lines and hold data;
- and
- a reversing circuit which logically reverses held data stored in the data storage units,
- wherein the data storage units are arranged at intersections of a pair of a first word line and a second word line, and a pair of a first bit line and a second bit line, and the reversing circuit is positioned between the pair of the first bit line and the second bit line, and controlled by a control signal.
Dependencies are inferred from the claim text.