Semiconductor storage device

A semiconductor storage device comprising:

• a memory cell array in which each of memory cells capable of holding data “0” or “1” according to a read level are arranged along row and column directions;
• a controller which counts the number of times N (N:
• an integral number equal to or more than 0) of sequentially writing the data into the memory cell and which transfers, to the memory cell, a write voltage and a read voltage which are variable according to the number of times N;
• and
• a voltage generator which generates the write voltage and uses this write voltage to write at least “1” bit data into the memory cell and which generates the read voltage and reads the at least “1” bit data from the memory cell,
• wherein when the N-th (≧2) write request is issued to the memory cell,
• the controller causes the voltage generator to generate the read voltage corresponding to an (N−1)th time, and uses this read voltage to read the “1” bit data from the memory cell,
• according to the data corresponding to the write request, the controller causes the voltage generator to generate the write voltage which changes a threshold voltage of the memory cell to higher a threshold voltage than a threshold voltage of the memory cell at which the data is read in the (N−1)th reading, and
• when the N has reached a prescribed value, the controller erases the data held in the memory cell.