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US 2012/0069680 A1Published application
Nand with back biased operation
AssigneeMicron Technology, Inc.
InventorsAkira Goda, Seiichi Aritome
Life of this patent
Estimating the term…
Abstract
Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts
Claims20
A memory device, comprising:
- an array of memory cells;
- a controller configured to perform a method comprising:
- applying a positive bias to a select gate of a string including a cell to be programmed;
- applying a positive bias to a data line selectably coupled to the string including the cell to be programmed;
- applying positive biases to control gates in the string including the cell to be programmed;
- and
- applying a programming voltage to a control gate of the cell to be programmed for a portion of the programming operation from a first program pulse to a last program pulse.
4 more elements
A memory, comprising:
- an array of memory cells;
- a plurality of string drivers, each of the plurality of string drivers having a plurality of transistors to drive voltages to access lines of the array;
- and
- a controller to control back biasing transistors of the string driver of a selected program block of the memory.
1 more element
A memory, comprising:
- an array of memory cells;
- circuitry for control and/or access of the array of memory cells, the control circuitry configured to:
- apply a first positive bias on each of a common source and non-selected data lines of a memory;
- apply a second positive bias on a selected data line of the memory;
- and
- apply a read voltage to access lines of the cells to be read.
3 more elements
A memory, comprising:
- an array of memory cells;
- circuitry for control and/or access of the array of non-volatile memory cells, the control circuitry configured to perform a method comprising:
- biasing a tub in which the cells to be erased are formed;
- and
- biasing control gates of the memory cells at a non-zero voltage wherein biasing the control gates at a non-zero voltage comprises biasing the control gates at a positive voltage.
2 more elements
A memory, comprising:
- an array of memory cells;
- a plurality of string drivers, each of the plurality of string drivers having a plurality of transistors to drive voltages to access lines of the array;
- a controller to control operation of the plurality of string drivers to bias global access lines and local access lines configured to be selectively coupled to memory cells in a block of memory selected to be erased at a positive voltage, and to bias global access lines and local access lines configured to be selectively coupled to memory cells in a block of memory not selected to be erased at a positive voltage.
A memory, comprising:
- an array of memory cells;
- a plurality of string drivers, each of the plurality of string drivers having a plurality of transistors to drive voltages to access lines of the array;
- and
- a controller to control operation of the plurality of string drivers to bias a data line selectively coupled to one of a plurality of strings at a non-zero voltage, and to apply a programming voltage to a control gate of the memory cell to be programmed.
1 more element
A memory device, comprising:
- an array of memory cells;
- a plurality of string drivers, each string driver comprising a first transistor configured to drive a source select gate line and a second transistor configured to drive an access line coupled to an isolation memory cell in a string of memory cells including a memory cell to be programmed, the first and second transistors sharing a common gate;
- and
- a controller to control operation of the memory device to sense, write, and erase the array.
1 more element
A memory device, comprising:
- an array of memory cells;
- a plurality of string drivers, each of the plurality of string drivers having a plurality of transistors to drive voltages to access lines of the array;
- and
- a controller to control operation of the plurality of string drivers to back bias a transistor configured to drive a data line selectively coupled to the memory cell selected for programming, and to bias a gate of the transistor to turn off the transistor during programming.
1 more element
A memory device, comprising:
- an array of memory cells;
- a plurality of string drivers, each of the plurality of string drivers having a plurality of transistors to drive voltages to access lines of the array;
- and
- a controller to control operation of the plurality of string drivers to bias a source selectively coupled to the string of memory cells at a non-zero voltage, and to bias a data line selectively coupled to the string at a selected data line voltage.
1 more element
A memory device, comprising:
- an array of memory cells;
- a plurality of string drivers, each of the plurality of string drivers having a plurality of transistors to drive voltages to access lines of the array;
- and
- a controller to control operation of the plurality of string drivers to bias a source selectively coupled to the string of memory cells at a non-zero voltage, to bias a data line selectively coupled to the string at a selected data line voltage, to apply a read voltage to the memory cell to be read, and to apply a pass voltage to other memory cells in the string.
1 more element
A memory device, comprising:
- an array of memory cells;
- a controller configured to:
- bias a data line selectively coupled to the string at a selected data line voltage;
- and
- bias another data line at a non-zero voltage, wherein the other data line is selectively coupled to another string of memory cells that is adjacent to the string selectively coupled to the data line biased at the selected data line voltage.
2 more elements
Dependencies are inferred from the claim text.