Nonvolatile memory device and erasure method thereof

A nonvolatile memory device comprising:

• a cell array comprising a plurality of memory cells wherein the memory cells have a desired threshold voltage distribution for a state of being erased, wherein the distribution spreads over between a lower bound verification voltage and an upper bound verification voltage;
• a voltage generator configured to provide a word line voltage and a bit line voltage to word lines and bit lines of the plurality of memory cells respectively;
• a write driver and sense amplifier configured to write data or read out data through bit lines of the plurality of memory cells;
• and
• a control logic configured to control the voltage generator and the write driver and sense amplifier to perform a post-erasure operation of selecting and erasing an over-programmed memory cell having a threshold voltage higher than the upper bound verification voltage.

A nonvolatile memory device comprising:

• a memory cell array comprising a plurality of memory cells wherein the memory cells have a desired threshold voltage distribution for a state of being erased, wherein the distribution spreads over between a lower bound verification voltage and an upper bound verification voltage;
• a voltage generator configured to supply bias voltages for an erasure operation of the memory cells;
• and
• a control logic configured to control the voltage generator and to perform the erasure operation including a pre-program operation, a post-program operation, and a two-step erasure operation so that the memory cells have the desired threshold voltage distribution for a state of being erased.