Back to results
US 2012/0069675 A1Published application
Reducing noise in semiconductor devices
AssigneeMicron Technology, Inc.
InventorsVishal Sarin, Frankie F. Roohparvar, Jung Sheng Hoei
Life of this patent
Estimating the term…
Abstract
The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.
Claims24
A semiconductor device comprising:
- an array of memory cells;
- and
- control circuitry coupled to the array, wherein the control circuitry is operable to:
- apply a reset voltage to a control gate of at least one selected memory cell for a time prior to sensing a state of the at least one selected memory cell;
- and
- apply a sensing voltage ramp from a start voltage to a stop voltage, to the control gate of the at least one selected memory cell, wherein the start voltage is greater than or equal to the reset voltage, and the stop voltage is equal to or greater than a sensing voltage associated with sensing an uppermost state of memory cells in the array.
3 more elements
A semiconductor device comprising:
- an array of memory cells;
- and
- control circuitry coupled to the array, wherein the control circuitry is operable to:
- apply a reset voltage to a control gate of at least one selected memory cell for a time prior to sensing a state of the at least one selected memory cell, wherein the reset voltage is equal to or less than a sensing voltage associated with sensing a lowermost state of memory cells in the array;
- and
- apply a sensing voltage ramp to the control gate of the at least one selected memory cell.
3 more elements
A semiconductor device comprising:
- an array of memory cells;
- and
- control circuitry coupled to the array, wherein the control circuitry is operable to:
- apply a reset voltage to a control gate of at least one selected memory cell for a time prior to sensing a state of the at least one selected memory cell, wherein the reset voltage is equal to or less than a sensing voltage associated with sensing a lowermost state of memory cells in the array, and wherein the time is sufficiently long to allow for charge detrapping in a dielectric interface of the at least one selected memory cell such that the at least one selected memory cell is in a state of accumulation;
- and
- apply a sensing voltage ramp to the control gate of the at least one selected memory cell.
3 more elements
A semiconductor device comprising:
- an array of memory cells;
- and
- control circuitry coupled to the array, wherein the control circuitry is operable to:
- apply a reset voltage to a control gate of at least one selected memory cell for a time prior to sensing a state of the at least one selected memory cell, wherein the particular reset voltage is sufficient to allow for charge detrapping in a dielectric interface of the at least one selected memory cell;
- and
- apply a sensing voltage ramp from a start voltage to a stop voltage to the control gate of the at least one selected memory cell, wherein the start voltage is greater than or equal to the reset voltage, and the stop voltage is equal to or greater than a sensing voltage associated with sensing an uppermost state of memory cells in the array.
3 more elements
Dependencies are inferred from the claim text.