Memory with interleaved read and redundant columns
AssigneeMicron Technology, Inc.
InventorsJin-Man Han, Aaron Yip
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsJin-Man Han, Aaron Yip
Estimating the term…
Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.
A memory device comprising:
An apparatus comprising:
An apparatus comprising:
Dependencies are inferred from the claim text.