Semiconductor storage device

Abstract

A memory includes plurality of word lines extending in a first direction, plurality of bit lines extending in a second direction to intersect with the word lines, and a memory cell array including plurality of memory cells connected to the word lines and the bit lines. Plurality of sense amplifiers include detectors configured to detect data transmitted from the memory cells to sense nodes via the corresponding bit lines, and capacitors connected between the sense nodes and a reference potential, respectively, and are provided to be arranged in the second direction from at least a side of one ends of the bit lines. Each of k capacitors corresponding to k detectors, where k is equal to or greater than 2, has a width corresponding to widths of the k detectors, the k capacitors are arranged in the second direction, and the k detectors are arranged in the first direction.

Dependencies are inferred from the claim text.