EEPROM-based, data-oriented combo NVM design

A method for forming a FLOTOX-based nonvolatile memory cell comprising:

• forming at least one floating gate tunneling oxide transistor on a substrate diffused with an impurity of a first conductivity type, wherein forming the floating gate tunneling oxide transistor comprises:
• diffusing an impurity of a second conductivity type to form a drain region,
• diffusing an impurity of a second conductivity type to form a source region,
• forming a channel region by separating the drain region and the source region,
• forming a gate insulation layer on the substrate over the drain region, the source region and the channel region,
• thinning an area of the gate insulation layer to form a tunneling insulation window over the channel region overlapping a portion of the drain region and the source region,
• forming a floating gate as a first conductive layer formed over the tunneling insulation window to allow charges to tunnel between the floating gate and the channel region and the drain region during a programming procedure and an erasing procedure of the FLOTOX-based nonvolatile memory cell, such that a floating gate to drain capacitance is determined by the width of the channel region and an overlap length of the an overlap of the floating gate over the drain region and a thickness of the tunneling oxide,
• forming an interlayer dielectric layer on the floating gate for providing electrical insulation to the floating gate, and
• forming a control gate of a second conductive layer on the interlayer dielectric layer such that a control gate to floating gate capacitance is determined by an area of the floating gate with the wing extension and a thickness of the interlayer dielectric layer;
• wherein a coupling ratio of the control gate to the floating gate and a coupling ratio of the floating gate to the drain are maintained as a constant as a space occupied by the FLOTOX-based nonvolatile memory cell is decreased by adjusting the length and width of the channel region and an length of the wing extensions.

A two-transistor NAND-like FLOTOX-based NOR nonvolatile memory cell on a substrate of a first conductivity type comprising:

• a pair of serially connected floating gate tunneling oxide transistors formed such that one of the pair of serially connected floating gate tunneling oxide transistors functions as a select gate transistor to prevent leakage current through the pair of floating gate tunneling oxide transistors when the pair of floating gate tunneling oxide transistors is not selected for reading, the pair of serially connected floating gate tunneling oxide transistors comprising:
• a first drain region and a second drain region formed of a diffused impurity of a second conductivity type, wherein the first drain region of a first floating gate tunneling oxide transistor is connected to a bit line associated with and parallel to the plurality of serially connected floating gate tunneling oxide transistors and the second drain region of the second floating gate tunneling oxide transistor is connected to a source line associated with and parallel to the pair of serially connected floating gate tunneling oxide transistors,
• a merged source region formed of the diffused impurity of the second conductivity type to form the source regions of the pair of serially connected floating gate tunneling oxide transistors,
• a first channel region separating the first drain region and the merged source region within the substrate,
• a second channel region separating the second drain region and the merged source region within the substrate,
• a gate insulation layer formed on the substrate over the first and second drain regions, the merged source region and the first and second channel regions,
• a tunneling insulation window formed of a thinned area of the gate insulation layer over the first and second channel regions and overlapping a portion of the first and second drain regions,
• a first floating gate of the first floating gate tunneling oxide transistor formed of a first conductive layer formed over the tunneling insulation window and having wing extensions that extend over a portion of the two shallow trench isolation regions, such that a first floating gate to drain capacitance is determined by the width of the first channel region and a first overlap length of the an overlap of the first floating gate over the first drain region and a thickness of the tunneling oxide,
• a second floating gate of the second floating gate tunneling oxide transistor formed of the first conductive layer formed over the tunneling oxide window and having wing extensions that extend over a portion of the two shallow trench isolation regions, such that a first floating gate to drain capacitance is determined by the width of the first channel region and a first overlap length of the an overlap of the first floating gate over the first drain region and a thickness of the tunneling oxide,
• a first control gate connected to a first word line and formed of a second conductive layer formed over the first floating gate and separated from the first floating gate by an interlayer dielectric layer such that a first control gate to floating gate capacitance is determined by an area of the first floating gate with the wing extensions and a thickness of the interlayer dielectric layer,
• wherein a coupling ratio of the first control gate to the first floating gate and a coupling ratio of the first floating gate to the first drain region are maintained as a constant as a space occupied by the two-transistor NAND-like FLOTOX-based NOR nonvolatile memory cell is decreased by adjusting the length and width of the first channel region and an length of the wing extensions of the first floating gate, and
• a second control gate connected to a second word line and formed of the second conductive layer formed over the second floating gate and separated from the second floating gate by an interlayer dielectric layer such that a second control gate to floating gate capacitance is determined by an area of the second floating gate with the wing extensions and a thickness of the interlayer dielectric layer,
• wherein a coupling ratio of the second control gate to the second floating gate and a coupling ratio of the second floating gate to the second drain region are maintained as a constant as a space occupied by the two-transistor NAND-like FLOTOX-based NOR nonvolatile memory cell is decreased by adjusting the length and width of the second channel region and an length of the wing extensions of the second floating gate.

A method for forming a two-transistor NAND-like FLOTOX-based NOR nonvolatile memory cell comprising:

• forming a pair of serially connected floating gate tunneling oxide transistors such that one of the pair of floating gate tunneling oxide transistors functions as a select gate transistor to prevent leakage current through the pair of floating gate tunneling oxide transistors when the pair of floating gate tunneling oxide transistors is not selected for reading, wherein forming the pair of serially connected floating gate tunneling oxide transistors comprises:
• diffusing an impurity of the second conductivity type to form a first drain region and a second drain region,
• diffusing an impurity of a second conductivity type to form a merged source region,
• forming a first channel region by separating the first drain region and the merged source region,
• forming a second channel region by separating the second drain region and the merged source region,
• forming a gate insulation layer on the substrate over the first and second drain regions, the merged source region and the first and second channel regions,
• thinning an area of the gate insulation layer to form a tunneling insulation window over the first and second channel regions overlapping a portion of the first and second drain regions,
• forming a first floating gate as a first conductive layer formed over the tunneling insulation window to allow charges to tunnel between the first floating gate and the first channel region and the first drain region during a programming procedure and an erasing procedure of the FLOTOX-based nonvolatile memory cell, such that a floating gate to drain capacitance is determined by the width of the channel region and an overlap length of the an overlap of the floating gate over the drain region and a thickness of the tunneling oxide,
• forming an first interlayer dielectric layer on the first floating gate for providing electrical insulation to the first floating gate,
• forming an second interlayer dielectric layer on the second floating gate for providing electrical insulation to the second floating gate,
• forming a first control gate of a second conductive layer on the interlayer dielectric layer such that a first control gate to floating gate capacitance is determined by an area of the first floating gate with the wing extension and a thickness of the interlayer dielectric layer,
• wherein a coupling ratio of the first control gate to the first floating gate and a coupling ratio of the first floating gate to the first drain are maintained as a constant as a space occupied by the FLOTOX-based nonvolatile memory cell is decreased by adjusting the length and width of the channel region and an length of the wing extensions,
• forming a second control gate of a second conductive layer on the interlayer dielectric layer such that a second control gate to floating gate capacitance is determined by an area of the second floating gate with the wing extension and a thickness of the interlayer dielectric layer,
• wherein a coupling ratio of the second control gate to the second floating gate and a coupling ratio of the second floating gate to the second drain are maintained as a constant as a space occupied by the FLOTOX-based nonvolatile memory cell is decreased by adjusting the length and width of the channel region and an length of the wing extensions.