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US 2012/0069629 A1Published application
Semiconductor memory device
OwnerYoshihiro UEDA, Akira KATAYAMA +1inventors
InventorsYoshihiro UEDA, Akira KATAYAMA, Ryousuke TAKIZAWA
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Abstract
According to one embodiment, a semiconductor memory device includes a first reference cell being arranged in a first cell array, and a plurality of first fuse cells being arranged in the first cell array. The first reference cell and the plurality of first fuse cells are arranged on the same row or column.
Claims19
A semiconductor memory device comprising:
- a first reference cell being arranged in a first cell array;
- and
- a plurality of first fuse cells being arranged in the first cell array, the first reference cell and the plurality of first fuse cells being arranged on the same row or column.
A semiconductor memory device comprising:
- a plurality of memory cells being arranged in a memory cell array;
- a reference cell being arranged in the memory cell array and storing reference data in read operation of the memory cell;
- and
- a fuse cell being arranged in the memory cell array and storing data with respect to a selection of the reference cell,
- wherein the reference cell and the fuse cell are electrically connected to a common reference word line or a common reference bit line.
2 more elements
Dependencies are inferred from the claim text.