Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device, comprising:

• a memory cell array including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of memory cells disposed at each of intersections of the first and second lines and each including a variable resistance element configured to store an electrically rewritable resistance value as data in a nonvolatile manner;
• a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the plurality of first lines according to a first address signal;
• at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to at least a portion of the first address signal and a second address signal;
• and
• a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

A nonvolatile semiconductor memory device, comprising:

• a memory cell array including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of memory cells disposed at each of intersections of the first and the second lines and each including a variable resistance element configured to store an electrically rewritable resistance value as data in a nonvolatile manner;
• a pair of first decoders connected to both ends of the plurality of first lines and configured such that one of the pair of first decoders selects at least one of the first lines;
• at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines;
• and
• a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.