US 2012/0069622 A1 · Sector Array Addressing for ECC Management

Abstract

An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.

Claims47

Dependent claims

A method of operating a memory array comprising:

providing a memory array, said memory array including a plurality of first conductive lines and a plurality of second conductive lines, each of said first conductive lines being coupled to one of said second conductive lines with a memory cell;
providing a first active drive, said first active drive charging said first conductive lines, said first active drive occurring while floating said second conductive lines;
terminating said first active drive and floating said first conductive lines.

Dependencies are inferred from the claim text.

Sector Array Addressing for ECC Management

Life of this patent

Sector Array Addressing for ECC Management

Life of this patent

Abstract

Claims47