Integrated Circuits Using Non Volatile Resistivity Sensitive Memory For Emulation Of Embedded Flash Memory

An integrated circuit (IC) including embedded non-FLASH non-volatile memory, comprising:

• a semiconductor substrate including circuitry fabricated on a logic plane of the semiconductor substrate, the circuitry including
• a data bus,
• an address bus,
• a control unit including FLASH emulation interface circuitry operative to electrically communicate with a first plurality of signals configured for data operations to FLASH memory, the first plurality of signals including a first address signal and at least one first data operation signal,
• a memory controller electrically coupled with the control unit, the address bus, and the data bus,
• an emulation interface circuitry operative to electrically communicate with a second plurality of signals configured for data operations to at least one non-FLASH memory type that is electrically coupled with the memory controller, the address bus, and the data bus, the second plurality of signals including a second address signal and at least one second data operation signal,
• an input/output (I/O) unit in electrical communication with the control unit and configured for electrical communication with an external system, the I/O unit operative to electrically communicate signals between the control unit and the external system,
• the data bus and the address bus are in electrical communication with the control unit and the I/O unit, and
• a logic block in electrical communication with the control unit and
• the I/O unit;
• at least one vertically configured memory plane in contact with and fabricated directly above the semiconductor substrate, the at least one vertically configured memory plane is positioned over the logic plane;
• a plurality of non-volatile memory arrays embedded in the at least one vertically configured memory plane, each non-volatile memory array including a plurality of two-terminal memory elements, each memory element (ME) having exactly two terminals comprised of a first terminal and a second terminal, each ME is operative to store at least one bit of data as a plurality of conductivity profiles that can be determined by applying a read voltage across the first and second terminals, the data is retained in the absence of electrical power, data is reversibly written by applying a write voltage across the first and second terminals,
• a first one of the plurality of non-volatile memory arrays is electrically coupled with the control unit and is configured for data storage use by the control unit, wherein the FLASH emulation interface circuitry is operative to perform data operations on the first one of the plurality of non-volatile memory arrays in response to the first plurality of signals and the data operations emulate FLASH memory data operations, and wherein the FLASH emulation interface circuitry is configured to perform a write operation to the first one of the plurality of non-volatile memory arrays without having to perform a FLASH erase operation prior to the write operation;
• and
• at least one other of the plurality of non-volatile memory arrays is operative as the at least one non-FLASH memory type, the at least one other of the plurality of non-volatile memory arrays is electrically coupled with the memory controller, the address bus, and the data bus, and wherein the emulation interface circuitry is operative to perform data operations on the at least one other of the plurality of non-volatile memory arrays in response to the second plurality of signals and the data operations emulate memory data operations to the at least one non-FLASH memory type.