Continuous-time sigma-delta analog-to-digital converter

A continuous-time delta-sigma analog-to-digital converter (ADC) comprising:

• a loop filter;
• a loop quantizer coupled to said loop filter;
• and
• a clock-jitter tolerant digital-to-analog converter (DAC) coupled to said loop filter and said loop quantizer, wherein said clock-jitter tolerant DAC includes
• a dual switched-current (SI) DAC for providing a first analog signal and second analog signal from a feedback digital signal of a loop quantizer within a delta-sigma analog-to-digital converter (ADC), wherein said first and second analog signals are substantially identical to each other;
• a switched-capacitor (SC) DAC for providing an error-free reference signal from said feedback digital signal;
• an adder for generating an inverted jitter induced error signal by subtracting said second analog signal from said error-free reference signal;
• and
• an injection circuit for providing a half-delay return-to-zero (HRZ) exponentially-decaying waveform based on a delayed version of said inverted jitter induced error signal.