Compensation of clock jitter in analog-digital converter applications

An apparatus for reducing clock jitter-induced error, comprising:

• a sample-and-hold module configured to receive a periodic analog reference signal and a clock signal having periods of successive clock cycles that vary according to clock jitter, the sample-and-hold module configured to provide an output sampled-and-held output signal;
• a numerically controlled oscillator configured to receive the same clock signal and to provide for each cycle of the clock signal a respective digital representation of the periodic analog reference signal;
• a digital-to-analog converter in electrical communication with the numerically controlled oscillator, the digital-to-analog converter configured to provide a respective analog output value responsive to each respective digital representation of the periodic analog reference signal;
• a difference module in electrical communication with the sample-and-hold module and the digital-to-analog converter, the difference module configured to determine for each cycle of the clock signal, a respective difference between each of the sampled-and-held output signal and the analog output value;
• and
• an analog-to-digital converter in electrical communication with the difference module and the clock signal, the analog-to-digital converter configured to convert each respective difference to a digital representation of the difference indicative of timing error of the respective cycle of the clock signal.

An apparatus for reducing clock jitter-induced error, comprising:

• means for obtaining at each cycle of a clock signal, a first sample of a periodic analog reference signal, the first sample including a sample error resulting at least in part from jitter-induced timing error of the clock signal;
• means for obtaining for each respective cycle of the clock signal a second sample of a discrete-time analog representation of the periodic analog reference signal, the second sample being substantially unsusceptible to jitter-induced timing error of the clock signal, each of the first and second samples corresponding to the same respective cycle of the clock signal;
• means for determining for each cycle of the clock signal a respective difference between each of the first and second samples;
• and
• means for converting the difference to a digital representation of the difference indicative of timing error of the respective cycle of the clock signal, the sample error.