Fast data weighted average circuit and method
AssigneeAsahi Kasei Microdevices Corporation
InventorsJeongseok Chae, Gabor C. Temes
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Abstract
A method and apparatus are provided for Fast Data Weighted Average (DWA) double-sampling modulators with minimal loop delay supporting improved stability. Quantization and DEM are accomplished within non-overlap time. By this reduction in time delay, power can be saved for analog integrators. The DC signal of partitioned DWA is removed by alternating reference voltages, and there is no additional delay as the alternation is performed at the comparator inputs. Embodiments employ an oversampling ratio (OSR) of 8 and a 15-level quantizer.
Claims20
A fast data weighted average circuit device comprising:
- an analog-to-digital converter (ADC) comprising a plurality of comparators;
- a data weighted average circuit comprising a shifter;
- wherein at least one of said plurality of comparators comprises an input signal and at least two switches per said at least one comparator, said at least two switches selecting between signals of at least a first block providing first reference voltages and signals of at least a second block providing second reference voltages as inputs to said plurality of comparators, based on a timing signal;
- wherein said shifter shifts said outputs of said plurality of comparators with n-gate delays, based on said timing signal, wherein said outputs of said plurality of comparators randomly direct to a plurality of outputs;
- wherein non-overlap alternation of said signals of said at least a first block and said at least a second block comprises double sampling quantization.
A delta sigma modulator comprising:
- an integrator;
- a fast data weighted average circuit device;
- and
- a digital-to-analog converter (DAC);
- wherein said fast data weighted average circuit device comprises an analog-to-digital converter (ADC) comprising a plurality of comparators;
- a data weighted average circuit comprising a shifter;
- and
- wherein said comparator comprises an input signal from said integrator and at least two switches per said comparator, said switches selecting between signals of at least a first block providing first reference voltages and signals of at least a second block providing second reference voltages as inputs to said plurality of comparators, based on timing signal;
- wherein said shifter shifts said outputs of said plurality of comparators with n-gate delays, based on said timing signal, wherein said outputs of said plurality of comparators randomly direct to a plurality of outputs, wherein said plurality of outputs provided to said DAC,
- wherein non-overlap alternation of said signals of said at least a first block and said at least a second block with double sampling quantization.
A fast data weighted average circuit device comprising:
- at least two switches per comparator, selecting between signals of at least a first block and signals of at least a second block providing reference voltages as inputs to a plurality of said comparators;
- and
- a critical path comprising a three-gate delay, whereby outputs of said plurality of comparators direct to a plurality of outputs, whereby non-overlap alternation of said signals of said at least a first block and said at least a second block with double sampling quantization and Dynamic Element Matching (DEM) removes DC components and maintains stability without introducing additional phase for the loop delay.
A method for fast data weighted average in a delta sigma modulator, said method comprising the steps of:
- selecting at least a first block;
- providing signal of said at least a first block to input of comparators;
- selecting at least a second block;
- and
- providing signal of said at least a second block to input of said comparators, wherein non-overlap alternation of double sampling quantization and Dynamic Element Matching (DEM) removes DC components and maintains stability without introducing additional phase for the loop delay.
Dependencies are inferred from the claim text.