Frequency Locking Oscillator
AssigneeAtmel Corporation
InventorsTor Erik Leistad, Frode Milch Pedersen, Fredrik Larsen
Life of this patent
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Abstract
A delay line of individually selectable delay elements can operate as an oscillator in an open loop mode to track process variation or drive a clock signal that varies with temperatures and voltages in the system. The delay line oscillator can also operate in a closed loop mode to match a frequency given by a tuner ratio and a reference clock. The delay line can also be used for measuring clock jitter or duty cycle.
Claims24
A system comprising an oscillator, wherein the oscillator comprises:
- a delay line comprising:
- a plurality of delay elements connected in a cascade from a first delay element to a last delay element;
- and
- a plurality of selecting elements configured to, for each delay element following the first delay element in the cascade, add or remove the delay element to a delay path through the delay line;
- a delay select register configured to store a value indicative of a total delay for the delay line, wherein the delay select register is coupled to each of the selecting elements;
- and
- an inverter configured to receive an output of the last delay element, wherein the inverter comprises an output coupled to the first delay element and the delay select register.
A method performed by a system comprising a oscillator, the oscillator comprising a plurality of delay elements connected in a cascade, each delay element comprising a standard cell selected from a library of standard cells, the method comprising:
- receiving a delay value;
- configuring a plurality of selecting elements to select delay elements to be included in a delay path through the delay elements, the delay path having a total delay based on the delay value;
- receiving an input signal at an input to the oscillator;
- inverting an output signal from an output of the oscillator and providing the inverted output signal to the input of the oscillator;
- and
- providing the output signal of the oscillator to a target device comprising another standard cell from the library of standard cells.
A method performed by a system comprising a delay line, the delay line comprising a plurality of delay elements connected in a cascade, the method comprising:
- receiving an input clock signal at an input to the delay line, the input clock signal having a period;
- configuring a plurality of selecting elements to define a delay path through the delay elements, the delay path having a total delay based on the period of the input clock signal;
- and
- for a number of clock cycles, incrementing a first counter if an edge of the input clock signal arrives at a counting circuit and an edge of an output signal of the delay line arrives at the counting circuit.
Dependencies are inferred from the claim text.